1. Field of the Invention
The present invention relates to communications buses for use in computer systems.
2. Related Art
Referring to FIG. 1, a prior art computer system 100 is shown in which three processors 102a-c communicate with each other over a communications bus 108. The processors 102a-c may, for example, be multiple processors within a single multi-processor computer, or processors in distinct computers communicating with each other over a network. As is well-known to those of ordinary skill in the art, processors 102a-c may transmit and receive data and/or instructions over the communications bus 108 using messages encoded according to a communications protocol associated with the communications bus 108. One example of a conventional communications bus is the Inter-IC (I2C) bus.
The processors 102a-c are coupled to bus transceivers 106a-c over local buses 104a-c, respectively. To transmit a message over the communications bus 108 (also called a “system bus” to distinguish it from the local buses 104a-c), a processor queues the message at the corresponding bus transceiver. For example, for processor 102a to transmit a message over the communications bus 108 to processor 102b, processor 102a must transmit the message over local bus 104a to the corresponding bus transceiver 106a, where the message is queued. Bus transceiver 106a then negotiates for control of the communications bus 108 in accordance with the bus protocol to become a bus master, and transmits the message over the communications bus 108 to the destination bus transceiver 106b. Bus transceiver 106b forwards the message to the destination processor 102b, and the originating bus transceiver 106a indicates to the processor 102a (by transmitting an appropriate message over the local bus 104a) that the message has successfully been sent.
Each new generation of multiprocessor computer tends to include a greater number of faster processors coupled to the bus 108 than the previous generation, thereby increasing the bandwidth demands placed on the bus 108. As the number and speed of processors connected to the bus 108 increases, it becomes increasingly important that the bus transceivers 106a-c process messages efficiently, accurately, and without hanging the bus 108.